3-D TSV: Insight On Critical Issues And

Market Analyses

Table Of Contents

Chapter 1 

Introduction

1-1

Chapter 2 

Insight Into Critical Issues

2-1

2.1

Driving Forces In 3-D TSV

2-1

2.2

Benefits of 3-D ICs With TSVs

2-2

2.3

Requirements For A Cost Effective 3-D Die Stacking Technology

2-3

2.4

TSV Technology Challenges

2-4

2.5

TSV Supply Chain Challenge

2-5

2.6

Limitations Of 3-D Packaging Technology

2-6

2.6.1

Thermal Management

2-7

2.6.2

Cost

2-9

2.6.3

Design Complexity

2-9

2.6.4 

Time To Delivery

2-14

Chapter 3 

Cost Structure

3-1

3.1

Cost Structure of D2W and W2W 3-D chip Stacks

3-1

3.2

Cost of Ownership

3-3

Chapter 4 

Critical Processing Technologies

4-1

4.1

Introduction

4-1

4.2

Cu Plating

4-2

4.3

Lithography

4-4

4.3.1

Optical Lithography

4-4

4.3.2

Imprint Lithography

4-5

4.3.3

Resist Coat

4-6

4.4

Plasma Etch Technology

4-7

4.5

Stripping/Cleaning

4-12

4.6

Thin Wafer Bonding

4-13

4.7

Wafer Thinning/CMP

4-19

4.8

Stacking

4-20

Chapter 5 

Evaluation Of Critical Development Segments

5-1

5.1

Introduction

5-1

5.2

Via-first Before FEOL

5-5

5.2.1

Equipment Requirements

5-5

5.2.2

Material Requirements

5-7

5.3

Via-first After FEOL

5-7

5.3.1

Equipment Requirements

5-8

5.3.2

Material Requirements

5-9

5.4

Via-Middle

5-9

5.4.1

Equipment Requirements

5-10

5.4.2

Material Requirements

5-10

5.5

Via-Last Before Bonding

5-12

5.5.1

Equipment Requirements

5-13

5.5.2

Material Requirements

5-14

5.6

Via-Last After Bonding

5-14

5.6.1

Equipment Requirements

5-15

5.6.2

Material Requirements

5-16

Chapter 6 

Profiles Of Participants

6-1

6.1

Chip Manufacturers/Packaging Houses/Services

6-1

ASE

ALLVIA

Amkor

austriamicrosystems

BeSang

Chartered Semiconductor

Cubic Wafer

Dai Nippon Printing

Elpida Memory

Freescale

Fujikura

IBM

Infineon

Intel

Jazz Semiconductor

Micron Technology

NEC

NXP

Oki Electric

Renesas

Samsung

Sharp

Silex Microsystems

Spansion

STATS ChipPAC

STMicroelectronics

Tessera

Tezzaron

Toshiba

TSMC

UTAC

Ziptronix

ZyCube

6.2 

Equipment Suppliers

6-38

Applied Materials

Datacon

ESI

EVG

Lam Research

NEXX Systems

PVA TePLA

Rudolph Technologies

Semitool

Suss MicroTec

Tegal

Tokyo Electron Ltd.

Ultratech

WRS Materials

6.3 

Material Suppliers

6-49

3M

Alchimer

Atotech

AZ

Brewer Science

Dow Chemical

DuPont Electronics

Enthone

Thin Materials AG

6.4 

R&D

6-56

3D Alliance

3D ASSM

A*STAR

CEA-Leti

EMC3D

Fraunhofer IZM

KAIST

Sematech

Chapter 7 

Market Analysis

7-1

7.1

TSV Device Roadmap

7-1

7.2

TSV Device Forecast

7-3

7.3

Equipment Forecast

7-8

7.4

Material Forecast

7-10

LIST OF TABLES

1.1

3-D Mass Memory Volume Comparison Between Other

Technologies And TI’s 3D Technology

1-8

1.2

3-D Mass Memory Weight Comparison Between Other

Technologies And TI’s 3D Technology

1-9

3.1

Cost Of Ownership Comparison

3-5

7.1

Forecast Of  TSV Devices By Revenues

7-4

7.2

Forecast Of  TSV Devices By Wafers

7-6

LIST OF FIGURES

1.1

3d Technology On Dram Density

1-2

1.2

3-D Through-Silicon Via (TSV)

1-6

1.3

Graphical Illustration Of The Silicon  Efficiency Between

MCMs And 3d Technology

1-10-

1.4

Silicon Efficiency Comparison Between 3D  Packaging

Technology And Other  Conventional Packaging Technologies

1-11

3.1

Cost Structure Of D2W And W2W

1-2

3.2

Cost Structure Of Different Vias And Tools

3-4

3.3

Via First (iTSV) Cost Of Ownership

3-7

3.4

Via First (iTSV) Cost Of Ownership Front And Back Side

3-9

3.5

Via First (iTSV) Process Flow

3-10

3.6

iTSV Versus pTSV Cost Of Ownership

3-11

3.7

Effect Of TSV Depth And Diameter On Cost

3-12

4.1

Illustration Of Bosch Process

4-9

5.1

Process And Equipment Flow For EMC3D Consortium Members

5-2

5.2

Various  TSV Integration Schemes

5-4

7.1

Leading Edge TSV Roadmap

7-2

7.2

Forecast Of  TSV Devices By Revenues

7-5

7.3

Forecast Of  TSV Devices By Wafers

7-7

7.4

Forecast Of  TSV Equipment

7-9

7.5

Forecast Of  TSV Materials

7-11