High-Density Packaging (MCM, MCP, SIP, 3D TSV): Market Analysis and Technology Trends

TABLE OF CONTENTS

Chapter 1 

Introduction

1-1

Chapter 2 

Executive Summary

2-1

2.1

Summary of Technology Issues

2-1

2.2

Summary of Market Forecasts

2-7

Chapter 3 

Technology Issues and Trends

3-1

3.1

Overview of HDP Technology

3-1

3.1.1

Need for Multiple IC Integration

3-7

3.1.2

Challenges of Multiple IC Integration

3-11

3.2

Technical Constraints of Integration

3-12

3.3

Economic Benefits of HDP

3-16

3.4

Technology Issues

3-20

3.4.1

Substrates

3-20

3.4.2

Conductors

3-35

3.4.3

Dielectrics

3-43

3.4.4

Vias

3-45

3.4.5

Die Attachment

3-48

3.4.6

Next Level Interconnection

3-57

3.4.7

Thermal Management

3-59

3.4.8

Test and Inspection

3-61

3.4.9

Design

3-67

3.5

3-D Modules

3-73

3.6

Superconducting Interconnects

3-76

3.7

Known Good Die

3-77

3.8

System In Package (SIP)

3-78

3.9

Multichip Package

3-84

3.10

Package-On-Package (PoP)

3-86

Chapter 4 

Applications

4-1

4.1

Overview of HDP Applications

4-1

4.2

Military and Aerospace

4-2

4.3

Computer and Peripheral Equipment

4-6

4.4

Communications

4-9

4.5

Consumer

4-12

4.6

Industrial

4-14

Chapter 5 

Competitive Environment

5-1

5.1

Overview of the HDP Competitive Environment

5-1

5.2

Joint Ventures and Cooperative Agreements

5-6

5.3

HDP Manufacturers

5-8

Advanced Packaging Systems

5-10

Aeroflex Laboratories

5-11

AMD

5-11

AMITEC

5-12

Amkor Electronics

5-13

Analog Devices

5-14

Appian Technology

5-15

AT&T

5-15

Ceramic Packaging

5-16

ChipSiP

5-16

C-MAC MicroTechnology

5-16

CNM-IMB

5-17

Conexant

5-17

Control Data

5-18

CTM Electronics

5-18

CTS

5-18

David Sarnoff Research Center

5-19

Delco Electronics

5-20

Digital Equipment

5-20

Elpaq

5-21

Elpida

5-21

ERIM

5-22

Eureka

5-22

Fujitsu

5-23

GEC Plessey

5-24

General Electric

5-24

Hadco

5-26

Honeywell

5-26

Hughes

5-27

Hynx

5-28

Ibiden

5-28

IBM

5-29

ILC Data Device Corp.

5-33

IMEC

5-34

Infineon

5-36

Interconnect Systems

5-36

Interconnex

5-37

International Micro Industries

5-37

Integrated System Assemblies

5-38

Intersil

5-39

Kodak

5-39

Kyocera

5-40

Lexmark International

5-41

Lucent Technologies

5-41

MicroModule Systems

5-43

Micron

5-45

Mitsubishi

5-46

Motorola

5-46

nCHIP

5-47

NEC

5-48

Pacific Microelectronics

5-49

Pacific Microelectronics Centre

5-49

Packard-Hughes Interconnect

5-50

Panda Project

5-51

Phillips Laboratory

5-51

Philips

5-53

Pico Systems

5-53

Quadrant Technology

5-54

Renasas

5-54

RISH

5-55

Rockwell Avionics

5-55

Rogers

5-56

S3

5-56

Samsung Electronics

5-57

Sensonix

5-58

Sharp

5-59

Sheldahl

5-59

Shinko

5-60

S-MOS Systems

5-61

Spansion

5-61

Spectra

5-62

Tektronix

5-63

Teledyne Electronic Technologies

5-63

Tessera

5-64

Texas Instruments

5-65

Thomson Consumer Electronics

5-68

Toshiba

5-68

TRW

5-68

United Technologies

5-69

White Electronic Designs

5-69

W.L. Gore & Associates

5-69

Z Systems

5-70

Chapter 6 

3-D-TSV Technology

6-1

6.1

Driving Forces In 3D-TSV

6-1

6.2 

3-D Package Varieties

6-11

6.3 

TSV Processes

6-17

6.4 

Critical Processing Technologies

6-19

6.4.1 

Plasma Etch Technology

6-23

6.4.2 

Cu Plating

6-24

6.4.3 

Thin Wafer Bondling

6-25

6.4.4 

Wafer Thinning/CMP

6-25

6.5 

Applications

6-26

6.6 

Limitations Of 3-DPackaging Technology

6-32

6.6.1 

Thermal Management

6-32

6.6.2

Cost

6-34

6.6.3

Design Complexity

6-35

6.6.4 

Time To Delivery

6-40

6.7 

Company Profiles

6-41

ASE

6-41

ALLVIA

6-41

Amkor

6-42

BeSang

6-45

Chartered Semiconductor

6-47

Cubic Wafer

6-48

Elpida Memory

6-48

Freescale

6-49

Fujikura

6-49

IBM

6-50

Infineon

6-51

Intel

6-52

Jazz Semiconductor

6-53

Micron Technology

6-54

NEC

6-56

NXP

6-57

Oki Electric

6-59

Renesas

6-60

Samsung

6-61

Sharp

6-63

Silex Microsystems

6-64

STATS ChipPAC

6-65

STMicroelectronics

6-66

Tessera

6-67

Tezzaron

6-69

Toshiba

6-72

TSMC

6-73

UTAC

6-74

Ziptronix

6-75

ZyCube

6-77

Chapter 7 

Market Forecast

7-1

7.1

Overview of Multichip Modules

7-1

7.2

Driving Forces

7-5

7.3 

Alternative Packaging Technologies

7-7

7.4

Worldwide IC Market Forecast

7-24

7.5

Worldwide Packaging Market Forecast

7-28

7.6

Worldwide MCM Market Forecast

7-31

7.6.1

Worldwide Forecast By Substrate Type

7-36

7.6.2

Worldwide 3-D Through Silicon Via (TSV) Market

7-39

7.6.2

Market Forecast By Application

7-43

7.6.3

Market Forecast By End Use

7-49

LIST OF TABLES

3.1

Multichip Modules Vs. Circuit Board Assemblies

3-17

3.2 

MCM Cost Comparison

3-19

3.3 

Substrate Technology Features

3-23

3.4 

Metal Conductors in MCMs

3-36

3.5 

Comparison of Thin-Film and Thick-Film Technologies

3-39

3.6 

Characteristics of Dielectric Materials

3-46

3.7

CTE of Common Substrates and Adhesives

3-55

3.8

Comparison of MCM Testers

3-66

3.9

Density Comparisons of Single Package and 3-D MCM

3-74

5.1

MCM Manufacturers

5-9

6.1

3-D Mass Memory Volume Comparison Between Other Technologies And Texas 3D Technology In Cm³/Gbit

6-5

6.2

3-D Mass Memory Weight Comparison Between Other Technologies And Texas 3D Technology In Grams³/Gbit

6-6

6.3

Institutions Working In The Area Of 3D TSV

6-16

6.4

Companies Working In The Area OF 3D TSV

6-17

7.1 

Worldwide IC Package Market Forecast

7-29

7.2 

Worldwide I/O Package Market Forecast

7-30

7.3 

Worldwide MCM Market

7-39

7.4 

Worldwide MCM-C Market By Application

7-45

7.5 

Worldwide MCM-D Market By Application

7-46

7.6 

Worldwide MCM-L (MCM, SiP, MCP) Market By Application

7-47

7.7 

Worldwide MCM Market By Application

7-48

7.8

Worldwide Market Forecast Of End Use Applications

7-52

LIST OF FIGURES

1.1

Schematic Cross-Section View Of An MCM-D

1-3

1.2

Cross-Section Of The RF And Microwave MCM-D Structure

1-5

1.3

Thin Film Layers On The Planarized Core Layer Of MCM-SL/D Technology

1-8

1.4

Flip Chip MCP

1-11

1.5

SIP Cross Section

1-14

3.1

IC Packaging Trends

3-2

3.2

Technology Tree For HDP Types

3-3

3.3

Form Factor Decrease By Package Type

3-10

3.4

High Power Package Technology Roadmap

3-32

3.5

Comparison Between Wire Bonding And Bump

3-50

6.1

3-D Through-Silicon Via (TSV)

6-3

6.2

Silicon Efficiency Comparison Between 3D Packaging Technology And Other Conventional Packaging Technologies

6-8

6.3

Comparison Between 2D And 3D Packaging Interms Of The Accessability And Useablity Of Interconnection

6-9

6.4

3D Packages

6-10

6.5

Through-Silicon Via (TSV)

6-18

6.6

Moore's Law For Active Element Density

6-25

7.1

Comparison Of SOC, MCM, SIP, And SOP

7-8

7.2

Materials Integrated In The SOP Concept

7-11

7.3

Digital, RF And Optical Function Integration In One SOP Package

7-12

7.4

Substrate Warpage Control

7-14

7.5

Effect Of Elastic Modulus On Sop Package Substrate Warpage

7-15

7.6

Area Assembly Pitch Reduction

7-17

7.7

Summary Of Package/Board Materials With Modulus And CTE

7-18

7.8 

Low Loss Dielectrics And Future Requirements

7-20

7.9

Eye Opening Measurements For Low Loss Dielectrics At 5 Gbps Data Rate

7-22

7.10

Projection of 3-D TSV Applications And Process Requirement

7-41

7.11

Market Forecast of 3-D TSV Wafers by Product

7-42